Particular embodiments generally relate to direct memory access (DMA).
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A buffer unit buffers data that is transferred between a system and an external codec (coder-decoder). The buffer unit includes a buffer where the data is temporarily stored during the transfer and also two small first in-first out (FIFO) devices placed between the buffer and the system. One of the FIFOs is for receiving data from the system to be stored in the buffer and the other one is for sending data from the buffer to the system.
A DMA controller is used to control the transfer of the data between the system and the FIFOs. The transfer of data to/from the buffer is controlled by logic that is part of or associated with the buffer. The logic generates a data request signal that is based on how much data is included in the buffer. When a data request signal is asserted, it is sent to a processor of the system, which then programs the DMA controller with information on how much data to transfer and also enables the DMA controller to transfer the data.
The FIFOs may be a receive FIFO (RX FIFO) and a transmit FIFO (TX FIFO). When the RX FIFO has space to receive more data, the RX FIFO issues a transmit request (TX request) to the DMA controller asking the system to transmit data to the buffer. Also, when the TX FIFO has room to transmit more data, the TX FIFO issues a receive request (RX request) to the DMA controller asking the system to receive data from the buffer. Logic for generating the RX or TX request operates independently from the logic that generates the data request signal. Thus, the TX FIFO or RX FIFO may be issuing TX or RX requests even when the buffer does not need to receive or send data.
One solution to limiting the TX or RX requests is to use the data request signal to indicate to the DMA controller when the TX and RX requests should be serviced. When the buffer is ready to receive data into the buffer or transmit data out of the buffer, the data request signal is asserted. The processor then programs the DMA controller with a certain number of TX or RX requests that can be serviced. For example, the DMA controller may be programmed to service 100 TX and/or RX requests. The DMA controller then services these 100 TX and/or RX requests and after the 100 TX and/or RX requests have been serviced, any further TX and/or RX requests are ignored until another data request signal is asserted. The above limits the number of TX and/or RX requests that can be serviced and does not allow a TX FIFO or RX FIFO to over-request for data transfers.
An interrupt is generated by the buffer unit to the processor when the data request signal is asserted. The processor then programs the DMA controller and enable it using an interrupt service routine. This requires some processor cycles and interrupts the processor from its normal operation.